1. Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having recess structure for increased channel length.
2. Description of the Prior Art
The conventional transistors having planar structures are unable to keep up with the technological demands of the recent advances in the integration of DRAM devices, such that, for example, these conventional transistors are unable to meet the required threshold target of the device in which the transistors are integrated. The advanced integration of DRAM devices requires reduction in the minimum feature size, and to reduce the minimum feature size the doping density is increased in a substrate, which inevitably increases the electric field as well as the function leakage in the transistor.
Therefore, a three-dimensional active structure called a “recess gate structure,” which is considered to having effects on lowering the substrate doping density and reducing the junction leakage, is newly emerging.
According to the conventional recess gate structure, an active area for formation of a gate is recessed, and a gate is formed on the recessed area of the active area, thereby increasing the channel length. Such conventional recess gate structure formed in the given active area may be able to reduce the substrate doping density, thereby increasing the data retention time. Further, the increase in the channel length (due to the recess channel structure in the given active area) can improve the characteristics with respect to the drain induced barrier lowering (DIBL) and the breakdown voltages (BVds), thereby may be able to improve the overall cell properties.
Because the recess channel structure is shown to extend the data retention time by, for example, more than 200 ms, it is expected that the recess channel structure be utilized in the DRAM devices below a level of the sub-90 nm.
As mentioned above, a gate having the recess channel structure formed on the recessed area of the active area is capable of increasing the channel length. However, when the given active area is reduced, the channel length will also have to be reduced even in the case of the recess gate structure undercutting the advantages gained. Thus, there will be less reduction of leakage current in the junction area and near elimination of the improvement in the refresh characteristics of the devices. As a result, it is impossible to secure consistent reliability and yield for the devices with reduced active area.